岗位职责:1、SoC system integration 2、 work with IP vendor (internal/external) to analyze integration issues 3、 SOC level LEDA, CDC check4、SOC level synthesis, STA, constraint generation,GCA, formal5、 interface to backend team on physical design and timing closure6、 interface to IP team on RTL quality

任职资格:1、minimum 3+/6+ years of ASIC design or integration experience 2、 solid working knowledge with front-end ASIC design flow and EDA tools (Verdi,Formality/LEC, DC, PT, Spyglass, etc.) 3、proficient in Verilog HDL 4、 familiar with DFT structure and flow 5、 good team work spirit Nice to have: 6、 familiar with low power flow(upf,vclp, etc.)