Job description
Common Essential Duties & Responsibilities
·         RTL-to-netlist generation through synthesis. Includes exploring different synthesis techniques to push frequency, area and improve power.  These techniques include RTL coding improvements, make trade-offs between different flop types to achieve best PPA, Vt recipes to explore dynamic and leakage power tradeoffs, identifying architectural useful skews, path group optimization, and many other techniques to produce a highly optimized gate level netlist.
·         Generate and maintain SDC constraints including and not limited to I/O, clock, exceptions, case analysis.
·         Formal verification of the netlist.
·         Exploring many different floorplans and optimizing P&R to deliver best in class design.
·         Optimize blocks using Structured Datapath design style (hand designed gates & placement). This includes working with the Special Circuits Organization to identify special cells for timing and power improvements, congestion relief, and pin alignment optimization.
·         Perform timing/power analysis and optimize paths to meet timing/power/area targets.
·         Implement functional ECO’s using formal tools or by hand.
·         Ability to work in a cross functional team environment and to be able to balance innovation and execution. Includes investigating new tools and design techniques.
·         Enjoys working in a collaborative work environment, sharing ideas, and learning from others.
 
Background / Experience 
·         BSEE or MSEE with 5 + years relevant experience.
·         Basic understanding of CPU architecture.
·         Solid understanding of CPU design/integration flow, timing constraints.
·         Hands-on experience with Synopsys DC/Primetime/ICC/ICC2/Formality and Cadence Conformal tools are a plus.
·         Knowledge of Verilog/System Verilog and ability to interpret the gate level implementation of different RTL structures.
·         Knowledge of Python, Perl, TCL, Shell, and other scripting languages.