岗位职责:1. Implements block level physical design, including floorplan, placement, CTS , routing, parasitic extraction, STA, Power analysis, Xtalk analysis, physical verification and ECO. 2. Solves block level timing, congestion, and IR/EM issues3. Work with full chip engineers to achieve timing closure for both partition and full chip level

任职资格:1. Bachelor or Master Degree in Engineering (Microelectronics, Electronics)2. 2+ years of hands on experience in large scale ASIC chip physical design3. Experienced with common EDA tools flow, ie: ICC/Innovus/Prime Time/Calibre4. Successful tape out experience is a plus5. Good teamwork and communication skills6. Familiar with scripting/programming (TCL, Perl, shell script, C)7. Language: Good English read/write