主要职责
1.Contribute as a design verification (DV) engineer within IC design team
2.Work with RTL, custom digital/analog, verification teams to implement and verify DFT functionality for various leading edge ICs
3.Work with cross functional groups to verify SOC implementation pre tape-out as well as drive successful bring-up of test features post tape-out

任职要求
1、211，985，海外名校以上学校（第一学历），硕士以上学历，​5年以上工作经验
2、Strong knowledge of digital design and SOC architecture
3、.Good understanding of OOP concepts
4、Experience in HVL such as System Verilog, UVM/OVM & System C
5、Experience in HDL such as Verilog
6、Scripting language like Perl, Tcl or Python
7、Analytical and Debugging skills
8、Low Power Design Verification Power Aware