Responsibilities:

• Be a part of the Central Analog Layout Team at Marvell china.
• Main responsibility is perform analog layout and related drc/lvs verification, debug and fix violations.
• Will be responsible for all levels of analog/mixed-signal layout from block level to AFE top level integration and physical verification.

• BS degree of electronic engineering, computer science with 5 years’ experience in IC layout
• Be familiar in high frequency analog/mixed-signal layout methods.
• Be familiar with 16/12/7nm technology, experience in 5nm is preferred.
• Be familiar with cadence virtuoso, synopsys laker and calibre drc/lvs.
• Good communication skills in written and verbal English.
• Good team work and communication skills. Hardworking and self-motivated under a high competition IP team.
• Good understanding of layout impact on device matching, noise coupling from signal, supply and substrate.
• Good understanding the importance of signal flow, power/ground structure and block placement in layout floorplan.
• Be familiar with SKILL/Perl/TCL program is preferred.