We are now looking for Mask Design Engineer for Digital IP team. The team develops the high performance digital IPs used in our chips. The main role is layout design for SRAM, ROM and STDcell using the most advanced IC process in the world.
What you’ll be doing:

• Develop digital IP layouts with excellent PPA in the most advanced process node
• Verify the layout in cell level and macro level
• Maintain the layouts per requests from circuit designers or other internal customers
• Create tools or scripts to improve work efficiency

• BS/MS in EE or equivalent experience
• Fundamental knowledge in digital logic, semiconductor device and manufacturing process
• Minimum 2+ years working experience on digital or mixed-signal layout design
• Familiar with Cadence design environment and ICV/Calibre verification tools
• Excellent communication in English
• Openness and team cooperation consciousness
• A passionate drive to deliver excellent works rather than complete tasks

• Background with Standard Cell or SRAM layout design
• Experience on layout design in 16/14nm node and beyond
• Knowledge in place and route
• Proficient user of Skill or Perl