We are now looking for a Methodology Engineer
The NVIDIA System-On-Chip (SOC) group is looking for a CAD/EDA programmer with an interest in developing the Padring design flow for a complex GPUs and SOCs. The ideal candidate for this position needs to has a strong programming skills as well as a broad ASIC and DFT knowledge.
What you’ll be doing:
- Be responsible for all aspects of the padring methodology work which includes maintaining existing padring RTL generation flow
- Providing support to the padring designers and DFT team, and owning the creation, implementation, and verification of the next-generation padring generation flow
- Interfacing with cross functional teams, such as : Physical Design, CAD, Package Design, DFT SOC Design System/Platform architecture , library memory and IO teams to understand the padring design
What we need to see:
- BS or MS (preferred) in EE/CE/CS.
- Strong coding skill skin Perl ,TCL,C /C++
- Understand ASIC design/implementation flow
- Proficient in DFT knowledges such as JTAG, BDSL, IEEE1500, etc.
- Fluent English (both written and spoken) and excellent communication skills to
- interface with many groups and build consensus
- Good team work spirit, easy to cooperate with team members
- Prior experience in floor planning and board level is a plus.
- Prior experience in implementing System-On-Chip is a plus
- Prior experience in RTL build and design automation is a plus
