芯驰科技

200-500人

上海市浦东新区亮秀路72号

芯驰科技

芯驰科技

STA Engineer

35万 - 65万 上海 | 3年以上 | 本科及以上 | 全职

职位福利:五险一金,福利好,老板nice,技术领先,成长空间大

发布时间:2021-08-28 发布者:Smiley 投递简历

描述:

岗位职责:

Responsibilities:
The candidate will work with RTL designers and backend engineers to create/review timing constraints, analyze timing, generate timing ECOs to close design timing. 



Requirements:
1. BS or above in EE, CS
2. 5+ years’ experiences in the area of static timing analysis of large scale deep submicron designs using EDA tools like Primetime or Tempus.
3. Good understanding of advanced timing methodology concepts like noise, cross-talk, Advanced OCV, statistical STA, multi-voltage domain timing etc.
4. Understand the impact of improving placement, routing, cell sizing, buffering, logic optimization, etc. to design timing
5. Independent work experience on multiple million gates SoC timing sign-off.
6. Familiar with scripting language, such as, Perl, Python, Tcl, Shell.
7. Experience of synthesis/LEC and flow build up.
8. Working knowledge of Verilog.
9. Good verbal and written communication skills.
10. Ability to work in a team environment.
11. Organized and motivated.

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