30万 - 60万 上海 | 3年以上 | 本科及以上 | 全职
职位福利:年终奖金,五险一金,福利好,老板nice,年度旅游,成长空间大,节日礼物
发布时间:2021-12-14 发布者：吴瑕 投递简历
岗位职责:
1、 Work with the global design team to do complex SOC physical implementation for deep submicron design.
2、 Participates in block level backend design for complex SOC designs.
3、 Responsible for RTL to GDS flow including CPF definition, logic/physical synthesis, die size estimation, floor-planning, power planning, CTS, place and route, STA, signal integrity, timing closure, formal verification, DFM, DRC/LVS etc.
4、 Play a critical role in high performance design timing closure.
