Responsibilities:
- Create the RTL architecture for the algorithm.
- RTL coding, new logic design, simulation, synthesis. 
- Work closely with algorithm engineer to develop/debug new IP. 

Requirements:
- Master degree, major in Electronic Engineering/Computer Science or other related discipline.
- Minimum 3 years’ relevant working experience on IP simulation and debug process using VCS and Verdi.
- Very familiar with the Verilog HDL language, know VHDL is a plus.
- Design and test experience on MCU controller design is a plus.
- Very familiar with digital design EDA tools such as DC,PT,Formality. 
- Familiar with the flow of the IC design. 
- Strong communication skills.