Description:
Sr. / Staff ASIC DFT design engineer 
Focus on DFT design & debugging of leading-edge large SoC. 
 
Qualifications:
1.   BS (MS preferred) in microelectronics, electrical engineering or equivalent with 5~8 years of DFT design experience, preferably with large SoC chips.
2.   Handy experience on scan, mbist, boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools and RTL/gate simulation. 
3.   RTL design and STA experience is a strong plus.
4.   ATE tester experience is a plus. 
5.   Good team work spirit and communication skill.