Synopsys

500-1000人

上海市长宁区长宁路1027号13-18楼

Synopsys

Synopsys

ASIC Digital Design Engineer

20万 - 40万 上海 | 工作经验不限 | 本科及以上 | 全职

职位福利:年终奖金,五险一金,技术领先,成长空间大,技能培训

发布时间:2021-09-13 发布者:HR 投递简历

描述:

岗位职责:

Job Title:ASIC Digital Design Engineer
Location: Shanghai

Job Description
- Seeking a highly motivated and innovative digital design engineer with strong theoretical and practical background in high-speed data - recovery circuits.
- Working as part of a highly experienced mixed-signal design team, the candidate will be involved in designing and maintaining current and next generation PCIe Gen5, USB 2/3 SERDES, SATA, 10G-KR and  products.
- The position offers excellent opportunity to work with an expert team of digital and mixed signal designers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance  tests on the test-chips.
- In addition, this is a great opportunity to work with a wide suite of in-house digital design and verification tools, including VCS, Design Compiler, PrimeTime, Tetramax and so on
 
Job Responsibilities:
-  Customer package creation and regression flow developed with Perl or TCL script.
-  RTL coding of high-speed digital circuits, modeling of analog blocks.
-  Writing verilog and system-verilog test-benches.
-  Synthesis, Defining place and route constraints, resolving STA issues and performing gate-level simulations.
-  Defining and debugging DFT structures in the designs for high DFT coverage.
-  Design Flow development as the DFT OCC, boundary scan flow, Spyglass flow.
-  Interacting with customer support and back-end design teams.

Job Requirements
- This position typically requires BS or MS plus at least 1-2 years of digital design experience in the industry as well as hands on experience in designing high-speed digital circuits, writing test-cases in Verilog and System Verilog, and familiarity with code quality metrics.
- Candidates must have a deep understanding of asynchronous clock crossings, DFT design methodologies, and synthesis implications of RTL. Knowledge of back-end synthesis tools DC/PT is a plus as are good organization and communication skills for interacting between different design groups and customer support teams.
- Candidates need to have the good learning ability and communication skill.
- Candidates needs to have the good script skill as Perl, TCL

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