This position will be leading a global team to develop timing constrain validation and DFT validation platform for Synopsys leading edge interface IP.

Position Responsibilities:
- Drive and work closely with RTL, implementation and methodology teams to establish a flow that brings the RTL and STA constraints into the in-house infrastructure for STA analysis
- Use the regression infrastructure to provide feedback to the RTL team on the timing-cleanliness of the design and the quality of the STA constraints themselves
- Participate in the discussions/reviews of the regression results to improve the correct and efficiency of the flow
- Be responsible for ATPG pattern generation with good DFT fault coverage

Requirements:
Must have BSEE in EE with 7+ years of relevant experience or MSEE with 5+ years of relevant experience in the following areas:
- Demonstrates good communication skills in both Mandarin and English
- Excellent skills in scripting and automation
- Experiences with timing/Synthesis constraints and floorplan-aware synthesis
- Knowledge of Verilog and IC design development cycle
- Demonstrates good analysis and problem-solving skills
- leadership experience, demonstrate strong desire to lead and drive for results
- Experiences and decent knowledge with DFT fault coverage analysis, tools and flow setup: Synopsys TetraMax, Z01X