Job Title：武汉校招- Digital Design/Verification Engineer (数字工程师)
Location：Wuhan


基本要求
- 微电子、电子工程、通信或相关专业研究生
Typically requires fresh master/PHD graduate with the major of microelectronics, telecommunication, Electrical/Electronic Engineering, or relevance
- 熟悉数字设计的基本流程，熟练使用Verilog语言对数字电路进行设计或SystemVerilog进行验证
Familiar with basic digital design flow, experience with Verilog language for digital design or SystemVerilog for verification
- 有使用过脚本语言，如TCL, Perl, Python等
Experience with TCL, Perl, Python, or other scripting languages
岗位关键词
- 从事的相关产品是接口控制器 (Interface controller) / 高速DDR PHY /静态存储器/处理器 (Processor) 等
The related products are Interface controller, High Speed DDR PHY, Static memory，Processor etc.
- 使用先进设计工艺（如5nm/7nm/10nm），从事数字设计，UVM验证，以及业内领先的开发流程相关工作，如Timing，DFT, Firmware等相关工作
Work on Digital Design, UVM Verification, and state-of-the-art implementation flow development including Timing, DFT and Firmware tasks with advanced technology (5nm/7nm/10nm).