40万 - 50万 深圳 | 5年以上 | 本科及以上 | 全职
职位福利:年终奖金,五险一金,技术领先,成长空间大,技能培训
发布时间:2021-09-13 发布者:HR 投递简历
岗位职责:
The candidate will be to work closely with Synopsys customers, enabling them to design embedded systems through the efficient use of our ARC CPU core offerings. The systems engineer will also investigate technical issues and answer in-depth technical questions about product configuration, system integration, RTL design & verification, firmware bringup, and hardware & software debugging. This position will also take an active role in presales engagements as a solutions architect, enabling ARC technology.
Requirements
- Masters/Bachelors graduates with 10-15 years experienced engineers are welcome.
- Tech requirements · RTL Coding (Verilog/System Verilog/System C). · Embedded systems programming.
· Experience with firmware for signal processing.
· Knowledge of at least one microprocessor/DSP architecture.
· Experience of hardware development using Verilog for ASIC or FPGA development including Usage of RTL coding (Verilog/System Verilog), logic simulation and synthesis, timing analysis, and verification methodologies.
· Strong problem solving ability and debug through verification capability.
· Excellent oral and written communication skills (English).
· Ability and desire to learn. Helpful qualifications:
· Previous customer facing experience desirable.
· Domain knowledge of ISS (instruction Set Simulator) and FPGA emulation
· Comfortable with System C or System Verilog Platform development.
· Knowledge of TCL/TK scripting language.
· Knowledge of silicon level implications on area, low power, and speed performance.
· Knowledge using compilers, linkers, assemblers and debuggers and run subset test programs on · CPU core in C/C++ and assembly code.
· Experience with a DSP CPU core and a DSP assembly language.
· Experience in creating customer oriented documentation through usage of commercial standards, such as FrameMaker or equivalent.