JD & Requirement
Synopsys verification solution team owns the responsibility to develop the total verification solution aiming the emerging semiconductor applications like 5G, AI and Automotive.
In this role, you will be part of the Asia-Pac regional verification solution team working with customers, field engineers and R&D. You will be developing the verification solutions based on Synopsys Verification Continuum technologies including virtual prototyping, static and formal verification, simulation, emulation and FPGA prototyping.

Requirements:
- This position requires a minimum of BSEE + minimum 6 years of related experience.
- Strong proficiency in one or more of Verilog, SystemVerilog & VHDL is required
- Experience in any of the emulation/FPGA platform or virtual prototyping is required
- Very good understanding of verification concepts with experience in any functional simulator is required
- Complex Problem solving and debugging skills are essential
- Knowledge about communication system will be a must
- Knowledge in Synopsys Tools like ZeBu, HAPs, Virtualizer, VCS, Verdi, etc will be a plus
- Experience in any of the scripting language is required
- Strong communication skills and ability to interact with customers as well as peers is required