Job Descriptions




1. This position is responsible for IP FPGA prototype work including IP core RTL integration, test bench creation for simulation with Verification IP, FPGA synthesis to achieve clean time result, hardware testing and debugging through hardware instruments.




2. Will be working with the IP core, PHY Design Engineering teams and Driver software engineer to understand the IP protocols and PHY application, to define and implement the integration architecture and test plan




3. Perform FPGA synthesis, define correct timing constraints, IO constraints to achieve time clean synthesis result




4. Will be involving all states of the prototype development process from the specification define, design implementation, simulation, FPGA synthesis, and hardware system verification.




Position Requirements




1. BSEE or MSEE (is preferable) with 3+ yrs of experiences in FPGA design and IC validation.

2. Must be proficient with Unix OS, Verilog HDL, Shell scripting.

3. Hardware validation and debugging experiences are highly desirable.

4. Knowledge of programming device driver in Linux/Windows system is plus.

5. Knowledge of the PCIe/USB/AMBA Protocol or relevant high speed interface protocol (specifications, compliance and interoperability testing, design/verification experience etc.) will be a definite plus.

6. Has strong desires to learn new technologies and demonstrates good analysis and problem-solving skills