Job Title: 上海校招-Digital IP Design Engineer
Location: Shanghai

Responsibility: 

• This position is for leading edge IP design.
• Study standard specifications published by JEDEC
• Define micro architecture at block level based on IP architecture
• Work on RTL design based on predefined coding style, SVA is also included
• Clean RTL check violations in lint, CDC, DFT and synthesis
• Run block level test to speed up IP verification
• Work with verification to debug and fix RTL issues
• Check synthesis timing and improve RTL design if required

• Be familiar with RTL design
• Be fluent in English, both speaking and writing
• Knowledge in software programming, e.g. C/C++, Python, is a plus
• Knowledge in any high performance interface technologies, e.g. DDR, PCIe, ethernet, is a plus
• Knowledge in any chip infrastructure, e.g. RISC, AMBA protocols, is a plus
• Has strong desire to learn and explore new technologies
• Demonstrates good attitude in team work