The ASIC Physical Design engineer is a challenging and cutting-edge position.  It has responsibility for a wide range of tasks, from RTL synthesis/floorplan till STA sign off, except DFT and P&R.

工作职责：
- Driving super high-speed IO PD work: PD friendly design, custom timing report/fixing scripts, timing eco and signoff.
             GDDR6: 8G+ frequency
             PCIE/NVLINK: core logic frequency 1.6G +
             HDMI/LVDS/USB/SDMMC/EMMC/SPI/I2C…
- Async check (CDC, async timing check, MTBF, etc.)
- RTL Analysis and Synthesis
- Formal verification and netlist quality analysis
- Physical Integration and early floorplan
- Constraint and hierarchical Static Timing Analysis & signoff
- Timing closure through eco (cowork with P&R owner)
- Clock timing, test timing.
- Develop and enhance related physical design flow.
- Develop ASIC-PD internal tools.

任职要求：
- BS or MS in Electrical Engineering or Computer Science
- Above 3 years of relevant ASIC experience ideally with a focus in timing constraint and closure.
- Excellent scripts skills
- Excellent written and verbal communication skills in English
- Ability to multiplex many issues, set priorities, and work in a team environment
- Keep up to date with leading edge technologies
- Drive things to be closed by co-working with variable team

加分项：
- Knowledge about ASIC design, especially those PD related.
- Basic knowledge about DFT, P&R.