工作职责
1. You will participate in the research of verification methodology to improve automation and productivity to produce Nvidia’s new high-quality state of the art products.
2. Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers.
3. You responses to build block/IP testbench based on UVM methodology.
4. The responsibilities includes building test run and regression flow. Triage failures in regression and help designer root cause the bug.
5. Work includes Build various metrics (passing rate, functional coverage, etc) and monitor its health.
6. Take SOC verification on fullchip test environment for IPs
7. Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score.
8. Deploy the advanced verification methodology and infrastructure of the SOC/IP

任职资格
1. BS / MS in electrical / computer engineering and related.
2. 3+ years (MS) or 5+ years (BS) working experience.
3. Familiar with advance verification methodology (UVM, VMM, OVM, etc), tools and flow
4. Fully experienced verification flow, including testplan, test, coverage model, testbench, BFM modeling.
5. Deep understanding in Verilog and HVL (High-level Verification Language)

加分项
1. Strong programming skills in Perl and C/C++is plus
2. Having good arch/design experience is big plus.
3. At least good at one of the script programing lanange : Perl, Shell, Ruby, Python, etc.
4. Fluent English (both written and spoken) and excellent communication skills
5. Proven ability to work independently as well as in a multi-disciplinary group environment
6. Strong analytical skills