25万 - 50万 上海 | 工作经验不限 | 本科及以上 | 全职
职位福利:年终奖金,五险一金,节日礼物,老板nice,福利好,年底双薪,年度旅游,技术领先,成长空间大,技能培训
发布时间:2020-12-05 发布者:陈雷雷 投递简历
岗位职责:
Job Responsibilities:
Logic Verification Engineer is working on cuttingedge Digital and Mixedsignal IP development for worldwide clients, including High Speed Serial Links, Protocols, Memory Interface, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in the frontend logic verification or mixed signal verification.
Requirements:
1. ME/EE/CS or background in related areas.
2. Research and/or development experience in one or more of the following areas:
● Logic verification on the basis of the target system specification
● Mixed signal model verification on advanced technologies
● Proficiency in programming and/or scripting languages is a plus
● Knowledge on Protocols, High Speed Serdes or DDR is a plus
3. Experience in one or more of the following application domains, is a plus
● High performance computing system, processor, chipset and ASICs
● High end communication, networking, mobile and data center applications
● Digital signal processing, sensor and Internet of Things
● Other emerging IT technology and industry areas
4. Good English skills, communication skills, and willingness to work with a global team.
5. Good learning competency, selfmotivated, and ability to work in diverse areas in a flexible and dynamic environment.
工作地点:上海、北京