JOB DESCRIPTION:
    
1. Work with SoC architecture team to define the top level clock structure of large scale SoC
    
2. Implement top level clock network with EDA tools and/or manual scripts
    
3. Implement top level power grids, including bumps/RDL metal layers/Mimcap
    
4. Perform circuit simulations and verifications to make sure the clock structure meets different specs, such as skew, latency, power, reliability
    
5. Perform initial IR/EM analysis to ensure a solid PG network
    
6. Working with different function teams to solve clock/power related issues
    
7. Develop top level clock and power design flow
    
    
QUALIFICATIONS:
    
1. BS/MS/Ph.D. Degree in Electrical/Electronics Engineering
    
2. 7+ years of hands on experience in large scale hierarchical SoC physical design
    
3. Experienced with common EDA tools flow, ie: ICC2/Innovus/Prime Time/Calibre
    
4. Experience in transistor level Spice simulation
    
5. Experience in top level clock implementation either in H-Tree or Mesh is a plus
    
6. Experience in PG network design is a plus
    
7. Proficient in scripting with TCL, perl, shell, python
    
8. Good verbal and speaking English