30万 - 60万 苏州 | 3年以上 | 硕士及以上 | 全职
职位福利:五险一金,年度旅游,成长空间大,技术领先,十五薪,技能培训,股票期权,老板nice,福利好
发布时间:2020-11-25 发布者：Peter 投递简历
岗位职责:
JOB DESCRIPTION:
1. Build SoC/IP level Spyglass/Synthesis/Timing Analysis/Formality Check/CDC flow
2. Do SoC/IP level synthesis / timing analysis / formality check / CDC check
3. Deliver constraints and closely co-work timing closure with P&R
4. Take some block level RTL coding
QUALIFICATION:
1. MSEE with ＞3 year+ experience of digital design experience;
2. Relevant experience in complex timing closure;
3. Be familiar with DC/PT/formality check tools
4. Be familiar with Tcl/Perl/…. Scripts language
5. RTL coding experience is a plus
