Job Responsibilities
ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in engineering implementation spec writing from system 
requirements, RTL design, verification, synthesis, static timing analysis.
Job Requirement
MS or PD in EE or CE with VLSI emphasis. Graduate from reputable university with competitive GPA or class ranking. Graduate course work in VLSI design, digital circuit theory, logic synthesis, logic design or computer architecture. Exposure to graduate school projects in ASIC design.
Must have good knowledge of ASIC design flow and UNIX-based EDA tools. Must have RTL experience including specification, design, verification and synthesis.
Must be proficient in the following skills:
Fundamental concepts in digital logic design 
Concepts digital logic timing analysis
Verilog/VHDL coding and Lint tools
Strong Perl and Tcl scripting skill

Highly desirable skills:
Synthesis using Synopsys or Cadence tools 
Timing analysis using Primetime
DFT concepts of Scan, BIST
Formal verification
Low power design
MATLAB and C/C++ based system simulation and evaluation
DSP function hardware implementation such as digital filter, equalizer, timing recovery functions
Circuit level or custom design experience

Good personal communication skills and team working spirit. Hardworking and motivated to be part of a highly competent design team.