Job Responsibilities:

• Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
• Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.

• MS degree of EE. 
• Familiar with Verilog RTL design and has experience of large digital ASIC project.
• Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
• Familiar with unix/linux and scripts (tcl, perl etc.)
• Fluent English on talking, presentation and writing documents. 
• Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.