岗位职责:"1、SOC front-end design, including clock, reset, system control, top interface2、Responsible for RTL quality and module level synthesis3、 Support DV for function verification4、Support software driver development"

任职资格:"1、 minimum 3+/6+ years of ASIC design, 2、 Proficient in Verilog HDL, knowledge of system architecture and design3、 Solid working experience with Arm architecture and AMBA 4、 Familiar with front-end design flow and EDA tools5 、Strong problem solving, communication skills and good team work spirit6、 solid knowledge in one of the following area: DDR/HBM Memory controller PCIE design GFX design"